An efficient two-level partitioning algorithm for VLSI circuits

Please use this identifier to cite or link to this item: http://ir.sinica.edu.tw/handle/201000000A/37608

Title:	An efficient two-level partitioning algorithm for VLSI circuits
Authors:	Cherng, Jong-Sheng Chen, Soo-Jie Tsai, Chia-Chun Ho, Jan-Ming
Issue Date:	1999-01-01
Conference:	Design Automation Conference(ASP-DAC \'99)
URI:	http://ir.sinica.edu.tw/handle/201000000A/37608
Appears in Collections:	資訊科學研究所

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