公開日期 | 題名 | 作者 | 關聯 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2015 | EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors | Hsiang-Yun Cheng; Matt Poremba; Narges Shahidi; Ivan Stalev; Mary Jane Irwin; Mahumut Kandemir; Jack Sampson; Yuan Xie | ACM Transactions on Architecture and Code Optimization 12(2),17:1-17:22 | |||
2014 | EECache: Exploiting Design Choices in Energy-Efficient Last-Level Caches for Chip Multiprocessors | Hsiang-Yun Cheng; Matt Poremba; Narges Shahidi; Ivan Stalev; Mary Jane Irwin; Mahumut Kandemir; Jack Sampson; Yuan Xie | ||||
2015 | Energy-Efficient Inclusion Properties for STT-RAM Last-Level Caches | Hsiang-Yun Cheng; Matt Poremba; Ivan Stalev; Yuan Xie; Jack Sampson; Mary Jane Irwin | Non-Volatile Memories Workshop (NVMW), 1-2 | |||
2016 | Exploiting and Accommodating Asymmetries in Memory to Enable Efficient Multi-core Systems | Hsiang-Yun Cheng | Pennsylvania State University Ph.D Thesis, 1-149 | |||
2016 | LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches | Hsiang-Yun Cheng; Jishen Zhao; Jack Sampson; Mary Jane Irwin; Aamer Jaleel; Yu Lu; Yuan Xie | ||||
2018 | LIRS: Enabling efficient machine learning on NVM-based storage via a lightweight implementation of random shuffling | Zhi-Lin Ke; Hsiang-Yun Cheng; Chia-Lin Yang | Computing Research Repository | |||
2010 | Memory Latency Reduction via Thread Throttling | Hsiang-Yun Cheng; Chung-Hsiang Lin; Jian Li; Chia-Lin Yang |