EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors

Please use this identifier to cite or link to this item: http://ir.sinica.edu.tw/handle/201000000A/36473

Title:	EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors
Authors:	Hsiang-Yun Cheng Matt Poremba Narges Shahidi Ivan Stalev Mary Jane Irwin Mahumut Kandemir Jack Sampson Yuan Xie
Issue Date:	2015-07
Relation:	ACM Transactions on Architecture and Code Optimization 12(2),17:1-17:22
URI:	http://ir.sinica.edu.tw/handle/201000000A/36473
ISSN:	http://gateway.isiknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=Drexel&SrcApp=hagerty_opac&KeyRecord=1544-3566&DestApp=JCR&RQ=IF_CAT_BOXPLOT
URL:	http://dl.acm.org/citation.cfm?doid=2756552
Appears in Collections:	資訊科技創新研究中心

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