http://ir.sinica.edu.tw/handle/201000000A/36335| Title: | Memory Latency Reduction via Thread Throttling |
| Authors: | Hsiang-Yun Cheng Chung-Hsiang Lin Jian Li Chia-Lin Yang |
| Issue Date: | 2010-12-04 |
| Conference: | ACM/IEEE International Symposium on Microarchitecture (MICRO) (Atlanta, Georgia USA : ACM/IEEE) |
| URI: | http://ir.sinica.edu.tw/handle/201000000A/36335 |
| URL: | http://ieeexplore.ieee.org/document/5695525/?arnumber=5695525 |
| Appears in Collections: | 資訊科技創新研究中心 |
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