公開日期 | 題名 | 作者 | 關聯 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2016 | LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches | Hsiang-Yun Cheng; Jishen Zhao; Jack Sampson; Mary Jane Irwin; Aamer Jaleel; Yu Lu; Yuan Xie | ||||
2018 | LIRS: Enabling efficient machine learning on NVM-based storage via a lightweight implementation of random shuffling | Zhi-Lin Ke; Hsiang-Yun Cheng; Chia-Lin Yang | Computing Research Repository | |||
2010 | Memory Latency Reduction via Thread Throttling | Hsiang-Yun Cheng; Chung-Hsiang Lin; Jian Li; Chia-Lin Yang |